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From iga...@apache.org
Subject [1/3] git commit: Make sure ATS' atomics also compile on Solaris CC
Date Thu, 20 Sep 2012 15:19:56 GMT
Updated Branches:
  refs/heads/master 00d48fab8 -> e4739f861


Make sure ATS' atomics also compile on Solaris CC

apparently Solaris CC isn't quite aware of how this whole
Template stuff works. This commit teaches it.


Project: http://git-wip-us.apache.org/repos/asf/trafficserver/repo
Commit: http://git-wip-us.apache.org/repos/asf/trafficserver/commit/e4739f86
Tree: http://git-wip-us.apache.org/repos/asf/trafficserver/tree/e4739f86
Diff: http://git-wip-us.apache.org/repos/asf/trafficserver/diff/e4739f86

Branch: refs/heads/master
Commit: e4739f8614dd7fe003f2d6cba05cf11ed86d8c86
Parents: d1d707b
Author: Igor Galić <i.galic@brainsware.org>
Authored: Thu Sep 20 17:18:37 2012 +0200
Committer: Igor Galić <i.galic@brainsware.org>
Committed: Thu Sep 20 17:18:37 2012 +0200

----------------------------------------------------------------------
 iocore/cluster/ClusterMachine.cc |    3 +-
 lib/ts/ink_atomic.h              |   46 ++++++++++++++++++++++++++++++---
 2 files changed, 44 insertions(+), 5 deletions(-)
----------------------------------------------------------------------


http://git-wip-us.apache.org/repos/asf/trafficserver/blob/e4739f86/iocore/cluster/ClusterMachine.cc
----------------------------------------------------------------------
diff --git a/iocore/cluster/ClusterMachine.cc b/iocore/cluster/ClusterMachine.cc
index 4607191..056d3a0 100644
--- a/iocore/cluster/ClusterMachine.cc
+++ b/iocore/cluster/ClusterMachine.cc
@@ -153,8 +153,9 @@ clusterHandlers(0)
 ClusterHandler *ClusterMachine::pop_ClusterHandler(int no_rr)
 {
   int64_t now = rr_count;
-  if (no_rr == 0)
+  if (no_rr == 0) {
     ink_atomic_increment(&rr_count, 1);
+  }
   return this->clusterHandlers[now % this->num_connections];
 }
 

http://git-wip-us.apache.org/repos/asf/trafficserver/blob/e4739f86/lib/ts/ink_atomic.h
----------------------------------------------------------------------
diff --git a/lib/ts/ink_atomic.h b/lib/ts/ink_atomic.h
index 7a59891..b22cf24 100644
--- a/lib/ts/ink_atomic.h
+++ b/lib/ts/ink_atomic.h
@@ -78,19 +78,56 @@ typedef vuint64_s *pvuint64_s;
 
 #include <atomic.h>
 
+/* see http://docs.oracle.com/cd/E19082-01/819-2243/6n4i098m6/index.html */
+
+// ink_atomic_swap(ptr, value)
+// Writes @value into @ptr, returning the previous value.
+template <typename T> inline T *
+ink_atomic_swap(volatile T * mem, T value) {
+  return (T *)atomic_swap_ptr((volatile void *)mem, value);
+}
+
+// ink_atomic_cas(mem, prev, next)
+// Atomically store the value @next into the pointer @mem, but only if the current value
at @mem is @prev.
+// Returns true if @next was successfully stored.
+template <typename T> inline bool
+ink_atomic_cas(volatile T * mem, T prev, T next) {
+  return prev == (T)atomic_cas_ptr((volatile void *)mem, (void *)prev, (void *)next);
+}
+
+template <> inline bool
+ink_atomic_cas<uint8_t>(volatile uint8_t * mem, uint8_t prev, uint8_t next) {
+  return prev == atomic_cas_8((volatile uint8_t *)mem, prev, next);
+}
+
+
+// ink_atomic_increment(ptr, count)
+// Increment @ptr by @count, returning the previous value.
+template <typename Type, typename Amount> inline Type
+ink_atomic_increment(volatile Type * mem, Amount count);
+
+template <> inline uint8_t
+ink_atomic_increment<uint8_t, int>(volatile uint8_t * mem, int count) {
+  return atomic_add_8_nv(mem, (int8_t)count) - count;
+}
+
 static inline int8_t  ink_atomic_swap(pvint8 mem, int8_t value) { return (int8_t)atomic_swap_8((pvuint8)mem,
(uint8_t)value); }
 static inline int16_t ink_atomic_swap(pvint16 mem, int16_t value) { return (int16_t)atomic_swap_16((pvuint16)mem,
(uint16_t)value); }
 static inline int32_t ink_atomic_swap(pvint32 mem, int32_t value) { return (int32_t)atomic_swap_32((pvuint32)mem,
(uint32_t)value); }
 static inline int64_t ink_atomic_swap(pvint64 mem, int64_t value) { return (int64_t)atomic_swap_64((pvuint64_s)mem,
(uint64_s)value); }
 static inline void *  ink_atomic_swap(vvoidp mem, void *value) { return atomic_swap_ptr((vvoidp)mem,
value); }
 
-static inline int ink_atomic_cas(pvint32 mem, int old, int new_value) { return atomic_cas_32((pvuint32)mem,
(uint32_t)old, (uint32_t)new_value) == old; }
-static inline int ink_atomic_cas(pvint64 mem, int64_t old, int64_t new_value) { return atomic_cas_64((pvuint64_s)mem,
(uint64_s)old, (uint64_s)new_value) == old; }
-static inline int ink_atomic_cas(pvvoidp mem, void* old, void* new_value) { return atomic_cas_ptr((vvoidp)mem,
old, new_value) == old; }
+static inline bool ink_atomic_cas(pvint32 mem, int old, int new_value) { return atomic_cas_32((pvuint32)mem,
(uint32_t)old, (uint32_t)new_value) == old; }
+static inline bool ink_atomic_cas(pvint64 mem, int64_t old, int64_t new_value) { return atomic_cas_64((pvuint64_s)mem,
(uint64_s)old, (uint64_s)new_value) == old; }
+static inline bool ink_atomic_cas(pvvoidp mem, void* old, void* new_value) { return atomic_cas_ptr((vvoidp)mem,
old, new_value) == old; }
 
 static inline int     ink_atomic_increment(pvint32 mem, int value) { return ((uint32_t)atomic_add_32_nv((pvuint32)mem,
(uint32_t)value)) - value; }
+static inline int     ink_atomic_increment(pvint32 mem, unsigned value) { return ((uint32_t)atomic_add_32_nv((pvuint32)mem,
(uint32_t)value)) - value; }
+static inline int     ink_atomic_increment(pvint32 mem, long value) { return ((uint32_t)atomic_add_32_nv((pvuint32)mem,
(uint32_t)value)) - value; }
 static inline int64_t ink_atomic_increment(pvint64 mem, int64_t value) { return ((uint64_s)atomic_add_64_nv((pvuint64_s)mem,
(uint64_s)value)) - value; }
+static inline int64_t ink_atomic_increment(pvint64 mem, int value) { return ((uint64_s)atomic_add_64_nv((pvuint64_s)mem,
(uint64_s)value)) - value; }
 static inline void *  ink_atomic_increment(pvvoidp mem, intptr_t value) { return (void*)(((char*)atomic_add_ptr_nv((vvoidp)mem,
(ssize_t)value)) - value); }
+static inline void *  ink_atomic_increment(pvvoidp mem, void* value) { return (void*)(((char*)atomic_add_ptr_nv((vvoidp)mem,
(ssize_t)value)) - (ssize_t)value); }
 
 /* not used for Intel Processors or Sparc which are mostly sequentally consistent */
 #define INK_WRITE_MEMORY_BARRIER
@@ -167,12 +204,13 @@ ink_atomic_increment<int64_t>(pvint64 mem, int value) {
   return ink_atomic_increment(mem, static_cast<int64_t>(value));
 }
 
-#endif
+#endif /* Special hacks for ARM 32-bit */
 
 /* not used for Intel Processors which have sequential(esque) consistency */
 #define INK_WRITE_MEMORY_BARRIER
 #define INK_MEMORY_BARRIER
 
+
 #else /* not gcc > v4.1.2 */
 #error Need a compiler / libc that supports atomic operations, e.g. gcc v4.1.2 or later
 #endif 


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